Devices that integrate one or several functions on a single chip have many applications such as monitoring a property of a fluid or a chemical reaction. Such devices, known as lab-on-chip devices, typically combine semiconductor sensors and microfluidic channels on a tiny scale.
However, there is a requirement for low-cost integration of different technologies, in particular CMOS/MEMS and microfluidics. Economies-of-scale especially driven by the semiconductor industry favour solutions based on unmodified commercial processes. The constraints dictated by the varying range of physical dimensions of the different components make wafer-level integration too costly for low-cost mass manufacture. For example, a typical Lab-on-Chip application may require CMOS components having an area in the region of 1-10 mm2, MEMS components in the region of 25-100 mm2 and microfluidics components in the region of 200-2500 mm2. Therefore integrating these at wafer level would be hugely wasteful to CMOS/MEMS technologies, as the common Lab-on-Chip area would be dominated by the requirements of interfacing fluids and external systems to the devices.
FIG. 1 of the accompanying drawings shows a cross-section of hybrid CMOS/microfluidics composite having bond-wires 10 and die 4 encapsulated using photo-patternable epoxy 2. The microfluidic chamber 11 is formed by the substrate 1 being fixed to the carrier substrate 8. Problems arise in wire-bonding the fine bond wires and the need to encapsulate them afterwards.
Encapsulating chips at die level typically requires depositing and processing photosensitive materials (such as certain epoxies and SU-8) onto composite assemblies (such as a package or substrate), which are wire-bonded to the die (see FIG. 1 of the accompanying drawings). A common challenge is to avoid damage to delicate bond-wires due to mechanical stress caused by fluid viscosity in addition to centrifugal forces in spin-coating. An alternative approach is to define the unexposed (i.e. chemical sensitive) area via a sacrificial material (eg. SU-8), or by accurately defining a frame and then potting the region between the frame and package using a UV-curable epoxy. This technique is often referred to as “Dam and Fill” encapsulation. Commercial chemical sensors use more complex process flows based on combining the above techniques with pre-fabricated housings to ensure robust isolation in addition to long-term stability. However these are very laborious and thus expensive to mass-produce. All these above-mentioned techniques however have two fundamental limitations: (i) an unwanted well (typically 200-300 μm depth) is formed inside the bondpad regions, and (ii) due to this relatively thick encapsulant build-up, the top surface is not perfectly planar. This causes sealing, adhesion, and alignment problems when overlaying microfluidic channels above, which often requires an intermediate levelling step.
Several technology-based packaging solutions have been proposed. However these typically require post-processing CMOS devices at wafer scale (i.e. before dicing). Flip-chip packaging methods can provide a robustly encapsulated, planar top surface, however the issue of “parasitic wells” above the chip surface is not overcome. The MIT/Lincoln Labs experimental 3D CMOS process based on multiple Silicon-on-Insulator (SOI) CMOS tiers allows for through-tier vias and since the silicon sits on an insulating substrate, the bondpads can be brought to the underside of the substrate, leaving the top-layer planar for chemical sensing purposes. This perhaps offers the most promising solution for future emerging technologies (expected to feature towards the end of Moore's law—when scaling from 22 nm to 10 nm). This is confirmed by IBM dedicating a complete issue to 3D CMOS in their flagship “IBM Journal of Research & Development”. However, this technology remains years from being commercially available, and even then is expected to remain relatively expensive (compared to bulk CMOS) and thus it will be limited to niche applications.
Once the sensor has been encapsulated, it is desirable to provide a microfluidic channel to bring the fluid to the sensor. These channels are typically formed in a substrate, which is separate from the sensor substrate. The two substrates are aligned and sealed to each other. As semiconductor sensors become progressively smaller with a finer pitch, there arise problems with aligning the microfluidic channels to the sensors. Poor assembly tolerances mean that there is a chance that the walls between the channels may obstruct a sensor and indeed there may not be a sensor in each channel. In mass production, microfluidic alignment tolerances may be 100-1000 times more than the minimum feature size of the sensor.
In some applications it may be desirable to monitor reactions in a number of fluidic chambers using ISFET sensors. It is desirable to pattern a number of ISFET sensors on a single silicon chip, and yet have different reactions happen above each sensor. This means that the surface of the chip must be encapsulated in such a way as to create multiple chambers which are fluidically sealed from each other so that their chemical components cannot intermix.
To provide a seal between sensors, it is expected that a layer of fluidic channels/chambers will be mounted on top of the electronic chip. This could be built or etched directly on the surface of the chip with photolithography, or alternatively could be built as a separate part via a variety of means and then attached to the chip as a subsequent step.
Either way, an apparent trade-off is created as the fluidic channels/chambers must be aligned to the sensors. There is incentive to make the sensors closely spaced, i.e. fine-pitched, to minimise the size and therefore cost of the silicon chip (and fluidics as well). However, there is a competing incentive to make the sensors further apart so that it is simpler to produce the fluidics and align them with the sensors.
Substrates are often aligned by either aligning one substrate to a datum line on the other (perhaps a physical protrusion) or by aligning visually overlapping marks on each substrate. The intention is that the two substrates are centre aligned or normally aligned, such that the chambers and sensors are symmetrically aligned about a centre line(s). This usually means that the midpoint of each sensor is aligned to the midpoint of each chamber. Thus the alignment tolerance from centre is usually the width of the chamber less the sensor width, after which point a portion of the sensing surface will not be exposed to the chamber. The alignment tolerance may be expressed as:Tolerance=±(Wc−Ws)/2  (1)
Where Wc,Ws represent respectively the Width of one chamber, Width of one sensor.
The following references provide background to lab-on-chip packaging:    U.S. Pat. No. 7,033,910: Method of fabricating multi layer MEMS and microfluidic devices on a substrate with layers of predetermined weak and strong bond regions, communication provided by edge interconnects between layers    U.S. Pat. No. 6,910,268: Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via. Not wireless, uses wired vias.    U.S. Pat. No. 7,207,728: Optical bond-wire interconnections and a method for fabrication thereof. Optical bond-wire interconnections between microelectronic chips, wherein optical wires are bonded onto microelectronic chips.    U.S. Pat. No. 6,443,179: Packaging of electro-microfluidic devices. Electrical connection is made to bond pads on the front of the MIC.    U.S. Pat. No. 6,531,342: Method for transverse hybrid loc package    U.S. Pat. No. 6,882,033: High density direct connect LOC assembly    U.S. Pat. No. 6,136,212: Polymer-based micro-machining for microfluidic devices    (WO/2003/107043) OPTOELECTRONIC ASSEMBLY WITH EMBEDDED OPTICAL AND ELECTRICAL COMPONENTS.    IPC8 Class: AH05K714FI, USPC Class: 361796: Interconnection and Packaging Method for Biomedical Devices with Electronic and Fluid Functions    E. Culurciello et. Al, “Capacitive Inter-Chip Data & Power Transfer for 3-D VLSI”, IEEE TCAS-II, Vol. 53, No. 12, 2006.    T. D. Strong, “Integrated Electrochemical Neurosensors”, IEEE ISCAS '06, pp. 4110-4113, 2006.    W. Oelßner, et al., “Encapsulation of ISFET sensor chips”, Sensors & Actuators B, Vol. 105, pp. 104-117, 2005.    L. Sudakov-Boreysha et al., “ISFET CMOS Compatible Design and Encapsulation Challenges”, IEEE Conference on Electronics, Circuits and Systems (ICECS '04), pp. 535-538, 2004.    “3D Chip Technology”, IBM Journal of Research and Development, Vol. 52, No. 6, 2008.    Vilches A, Sanni A, Toumazou C, Single coil pair transcutaneous energy and data transceiver for low power bio-implant use, IET ELECTRONICS LETTERS, 2009, Vol: 45, Pages: 727-U25, ISSN: 0013-5194.
It is an object of the present to provide apparatuses and methods overcoming the problems with the present techniques as discussed above.